From the miniaturization of existing systems (position sensors, labs on chip ...) to the creation of specific integrated functions (memory, RF tuning, energy ...), MEMS and non-electronic devices are being integrated to create heterogeneous systems in package (SiP) and systems on chip (SoC). This approach for future systems, classically termed as "More than Moore", will have significant impact on several economic sectors and is driven by
While the general benefits appear to be clear, this evolution represents a strong paradigm shift for the semiconductor industry, as obstacles to transistor scaling (both fundamental and economic) also push the focus towards increasing diversification. This shift away from a trend that has lasted over 40 years is possible because the fabrication technology (or at least the individual technological steps) exists to do so; however, the capacity to translate system drivers into technology requirements (and consequently guidance for investment) to exploit such diversification is severely lacking. Such a role can only be fulfilled by a radical shift in design technology to address the new and vast problem of heterogeneous system design while remaining compatible with standard "More Moore" flows.
The main objective of such an evolution is to reduce the design time in order to meet time to volume constraints. It is widely recognized that for complex systems at advanced technology nodes, a radical evolution in design tools and methods is required to reduce the "design productivity gap". Production capacity increases annually by around 50%, while design capacity increases annually by a rate of only 20-25%. The 2003 and 2005 ITRS Roadmaps (and intermediate updates) both clearly state that "Cost [of design] is the greatest threat to continuation of the semi-conductor roadmap. ... Today, many design technology gaps are crises". Without the introduction of new design technology, design cost becomes prohibitive and leads to weak integration of high added value devices (such as sensors and RF circuits) for the various application sectors (automotive/transport, biomedical, telecommunications ...).
In this context, we are working on a framework for multi-domain and multi-abstraction level synthesis called RuneII (PRTP Osmose, Jacques Cartier, Nano2008). Collaborations: CEA-LETI (France), STMicroelectronics (France), Ecole Polytechnique de Montréal (Canada).
The emergence of very high performance SoC is necessary to achieve future required application performance in terms of resolution (audio, video and computing) and CPU power / total MIPS (real-time encoding-decoding, data encryption-decryption). The shift to distributed multi-processor architectures is the recognized route to such performance and therefore requires organized high-speed communication between processors. Metallic interconnect will be highly inefficient in this role due to unachievable tradeoffs between design parameters (the main limitations due to metallic interconnects are inter-line crosstalk, latency, global throughput, connectivity and power consumption).
The concept of integrated optical interconnect is a potential technological solution to alleviate some of these issues involved in exchanging data between cores in SoC architectures. Our work aims to contribute to the ongoing assessment of the suitability of integrated optical interconnect for on-chip data transport.
Based on tools developed in the "Design methods for heterogeneous SoC and SiP" thematic, we have explored simulation-based quantitative comparisons of electrical to optical interconnects at the physical link level (RMNT Heteropt, FP6-IST PICMOS). We are currently working on concurrent physical and system-level evaluations for optical networks on chip, enabling high bandwidth and low contention routing of data using wavelength multiplexing (ACI Lambdaconnect, FP7-ICT WADIMOS). Collaborations: CEA-LETI (France), IMEC (Belgium), STMicroelectronics (Italy), Ecole Polytechnique de Montréal (Canada).
In order to pursue Moore's law and to achieve the computing capacities necessary for future software applications, it is today widely recognized that current systems on chip (SoC) will initially evolve towards multiprocessor systems on chip (MPSoC), then towards reconfigurable platforms. This vision, as stated by the European technological platform ARTEMIS, represents the structuring, necessary for future systems design, of several tens of billion of elementary devices. These systems will be used in the majority of economic sectors and in particular for high-performance computing (analysis and modeling of complex phenomena, advanced human-machine interaction) and for low-power mobile systems (sensor networks, ...)
The reconfigurable approach to computing systems comprises several advantages. It allows volume manufacturing and thus constitutes a solution to the projected evolution of mask costs (above $10M in 2011; above $100M in 2018 according to the ITRS). Such systems can cover a broad range of applications, and their performance levels very clearly exceed those of programmable systems in terms of computing speed, while requiring only one set of masks. Moreover, the natural association of these architectures with fault-tolerant design techniques makes it possible to build robust architectures in the context of increasingly unreliable elementary nanometric CMOS devices. Nevertheless, the various types of reconfigurable circuits (FPGA, coarse-grain reconfigurable systems) are at a disadvantage (compared to "full-custom" solutions) in terms of performance and device count necessary to fulfill a specific function.
In this context, the emergence of new devices offers the opportunity to provide novel building blocks, to elaborate non-conventional techniques for reconfigurable design and consequently to reconsider the paradigms of architecture design. The concept of ultra-fine grain reconfigurability enables benefits in terms of silicon real estate, since it makes it possible to reduce the number of logic cells necessary to implement a given switching function (in comparison with the implementation of these functions with conventional CMOS logic). Moreover, it makes it possible to reduce the interconnect network, which also reduces area and also the parasitic capacitances due to routing (of the interconnect network). It thus significantly reduces dynamic power dissipation and improves speed. These two performance metrics are often the weak point of programmable circuits in comparison with "full-custom" circuits because they are worsened by the parasitic capacitances of the interconnect network.
Recent technological breakthroughs have led to the advent of advanced multiple gate devices in both planar (DG MOSFET) and vertical dispositions (FinFET), as well as, more prospectively, emerging devices such as carbon nanotube transistors (CNTFET) or nanowire transistors (NWFET). Such devices, with four accessible terminals, open the way to solutions specifically exploiting the additional terminal for reconfigurability purposes.
We are currently developing reconfigurable cells based on double-gate CNTFETs (ACI Nanosys) and on double-gate MOSFETs (ANR PNANO Multigrilles). Collaborations: CEA-LETI (France).