Cédric Marchand

Associate Professor

"Maitre de conférences classe normale" (MCF CN)
Ecole centrale of Lyon , Institute of Nanotechnologies of Lyon , Electronic group
Keywords: Emerging technologies, Hardware security, Computing architectures

Resume

About Me

I am Associate Professor at “École Centrale de Lyon” and member of the electronic team of the Lyon Institute of Nanotechnology (UMR CNRS 5270) since 2017 and IEEE member since 2018.

I receive my engineering degree in Micro-Electronics and Applications from “École Nationale Supérieur des Mines de Saint-Étienne (Campus Gardanne, ISMIN)” in 2013.

I receive my Ph.D. from the University of Lyon in 2016, for a work entitled “Salutary hardware design to fight against counterfeiting and theft of integrated circuits”, which was supported by the ANR JcJc project SALWARE (number ANR-13-JS03-0003). I have been rewarded for this work by the PhD prize of excellence of the Jean-Monnet University foundation.

Today, my research interests focus on the study of the Hardware Security impact of heterogeneous systems that include emerging technologies in the context of the Internet of Things:

Experience

Associate Professor - Ecole centrale of Lyon
Sept 2017 - present
Institute of nanotechnology of Lyon

I am currently working as an associate professor at Ecole centrale of Lyon and at the Institute of nanotechnology of Lyon.

  • Research: I am part of the Electronic team of the laboratory and currently in charge of the working group on simulation and of the Reliable Ultra-low power Secure compuTing (RUST) group of the team. My research activities aim at evaluating the impact of emerging technologies on the hardware security of computing architectures.
  • Teaching: I am part of the EEA teaching department of Ecole centrale of Lyon and involved in the 3 year of the enigneering formation and part of the EEA department council. I am in charge of 1 first year lecture, 2 second year module and 1 third year module.
PostDoc Researcher - Hubert Curien Laboratory
Nov 2016 - Aug 2017
SESAM team

I worked as PostDoc researcher in the SESAM team of the Hubert Curien laboratory in Saint-Etienne. As a researcher, I was involved in the TEEVA project aiming at evaluating the security of the Arm Trustzone technology integrated inside System on Chip comprising both processors and FPGA. For this project I took part on the following tasks:

  • Setting up the Arm Trustzone in SoC device such as Xilinx Zynq and Intel Cyclone V FPGA.
  • Attacks on the system in form of modification of the communication protocol between the processor and the FPGA linked to the Trustzone integration.

Education

2013 - 2016
PhD in microelectronics
University of Lyon, Saint-Etienne, France

This PhD thesis has been carried out in the framework of the SALWARE project and had for main objective to fight against countergeiting and theft of integrated circuit. Three main area have been studied :

  1. The insertion of a watermark inside finite states machines and the possilibility to remotely verify the watermark using side channel analysis.
  2. The implementation and evaluation of an physical unclonable funtion (PUF) inside FPGAs
  3. The implementation of lightweight cryptographic algorithm on FPGA and ASIC.

This last part has been partially carried out under the supervision of professor Kris Gaj from George Mason University in which I was invited for 3 month.

This PhD has received the PhD excellence prize from “Fondation Univesité Jean-Monnet” of Saint-Etienne.

2011 - 2013
Engineering degree in microeletronics and application
Ecole des Mines de Saint-Etienne, Cycle ISMIN, Gardanne, France
This formation from “Ecole des Mine de Saint-Etienne” is specialized in embedded system and microelectronics.

Research projects

SECRET
ANR Coordinator HW security Emerging technology
SECRET
The ANR JcJC SECRET project aims at designing secure processor using emerging ferroelectric technologies.
More
PHASEPUF
ANR HW security Emerging technology
PHASEPUF
The ANR PHASEPUF aims at designing and evaluating a new PUF based on silicon photonic technology.
URL
FVLLMONTI
H2020 AI architecture Emerging technology
FVLLMONTI
The European H2020 FVLLMONTI objective is to develop regular 3D stacked hardware layers of NNs empowering the most efficient machine translation thanks to a design-technology co-optimization (DTCO) approach.
URL
NEUROPULS
Horizon Europe AI architecture Emerging technology Hw security
NEUROPULS
The european project NEUROPULS aims at developping secure hardware accelerators based on novel neuromorphic architectures and PUF-based security layers leveraging the benefits offered by the integration of photonics, PCMs and III-V materials.
URL
Ferro4EdgeAI
Horizon Europe AI architecture Emerging technology
Ferro4EdgeAI
The european project Ferro4EdgeAI to design a very low-power, scalable peripheral accelerator for artificial intelligence, incorporating a neural network with augmented memory, based on a low-cost, high-density, multi-level ferroelectric (FE) technology integrated circuit.
URL
ECHOES
ANR Hw security Emerging technology
ECHOES
The objective of the ANR project ECHOES is to determine whether hafnia-based FE NVM can outperform current NVM solutions for edge-security applications.
URL
HiLoDa Nets
ANR Circuit synthesis Emerging technology
HiLoDa Nets
The ANR project HiLoDa Nets objective is to combine high clock-speed data processing of each synthesized actor circuit in power-on mode and automatic state retention using FeFET technology in power-off mode, self-triggered during time intervals of either data unavailability or power shortage.
URL
FERROFUTURES
PEPR AI architecture Emerging technology
FERROFUTURES
The PEPR project FerroFutures aims at Highlighting the advantage of combining HZO-based FeRAM devices with a specialized unit for real-time, low-power consumption processing. This corresponds to the concept known as Compute-In-Place, which involves preprocessing data from various sensors to perform data fusion, filtering, or anomaly detection.
URL

Past Research project

LEGO
2018-2021
3eFerro
2018-2021

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