Publications

Key indicators

  • Journals: 9
  • Conférences: 17
  • Book Chapter: 3
  • Invited presentations: 9

  • h index: 9
  • i10 index: 7

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Journals Conferences Book Chapter Keynotes Workshops and Posters

Articles published in international Journals

  1. A. Ram, K. Maity, C. Marchand, et. al., Multifunctional van der Waals Ferroelectric Devices and Logic Circuits, in ACS Nano, october 2023, doi: https://doi.org/10.1021/acsnano.3c07952, arXiv: https://doi.org/10.48550/arXiv.2310.14648
  2. S. Mannaa, A. Poittevin, C. Marchand, et. al.Logic circuit design oriented electrothermal modeling of vertical junctionless nanowire FETs, in IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, August 2023, doi: 10.1109/JXCDC.2023.3309502
  3. C. Marchand, I. O’Connor, M. Cantan, et. al.A FeFET-based hybrid memory accessible by content and by address, in IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 8, no. 1, pp. 19-26, June 2022, doi: 10.1109/JXCDC.2022.3168057
  4. D. Navarro, C. Marchand and L. Carrel. Study of a Battery-less Near Field Communicating Sensor Network with ContactLess Simulator. International Journal On Advances in Telecommunications (IJOAT), IARIA, 2018. doi : hal-01971689.
  5. C. Marchand, L. Bossuet, U. Mureddu, et. al., Implementation and Characterization of a Physical Unclonable Function for IoT: A Case Study With the TERO-PUF in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 1, pp. 97-109. 2018. doi : 10.1109/TCAD.2017.2702607.
  6. C. Marchand, L. Bossuet, and K. Gaj, Area‐oriented comparison of lightweight block ciphers implemented in hardware for the activation mechanism in the anti‐counterfeiting schemes. Int. J. Circ. Theor. Appl., 45: 274– 291. 2017 doi: 10.1002/cta.2288
  7. E. Jung, L. Bossuet, S. Choi and C. Marchand, Identification of IP control units by state encoding and side channel verification, Microprocessors and Microsystems, Volume 47, Part A, Pages 11-22, ISSN 0141-9331, 2016 https://doi.org/10.1016/j.micpro.2016.02.019
  8. A. Cherkaoui, L. Bossuet and C. Marchand, Design, Evaluation, and Optimization of Physical Unclonable Functions Based on Transient Effect Ring Oscillators, in IEEE Transactions on Information Forensics and Security, 2016 vol. 11, no. 6, pp. 1291-1305. doi: 10.1109/TIFS.2016.2524666
  9. C. Marchand, and J. Francq, Low-level implementation and side-channel detection of stealthy hardware trojans on field programmable gate arrays. IET Computers & Digital Techniques, 8(6), 246-255, 2014 doi: https://doi.org/10.1049/iet-cdt.2014.0034
Top Conferences Book Chapter Keynotes Workshops and Posters

Articles published in international Conferences

  1. R. Bishnoi, S. Diware, A. Gebregiorgis, et. al., Efficient and Reliable Hardware Architectures based on Vertical Nanowire FETs, in proceedings of the International Conference on Microelectronics 2023 (ICM), Abu Dhabi, UAE, doi: 10.1109/ICM60448.2023.10378889
  2. A. Nicolas, C. Marchand and D. Navarro, Non Volatile Operators Emulation Platform, to appear in Proceedings of the 18TH ACM International Symposium on Nanoscale architectures (NANOARCH) 2023, Dresden, Germany. doi: to come
  3. C. Marchand, A. Nicolas, P.A. Matrangolo, et. al., FeFET based Logic-in-Memory design methodologies, tools and open challenges, in Proceedings of the 30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC) 2023, Oct 2023, Sharjah, United Arab Emirate, doi: 10.1109/VLSI-SoC57769.2023.10321901
  4. S. Mannaa, C. Marchand, D. Deleruyelle, et. al., VNWFET-Based Technology: From Device Modelling to Standard Cell Library, 2023 IEEE 23rd International Conference on Nanotechnology (NANO), Jeju City, Korea, Republic of, 2023, pp. 576-581, doi: 10.1109/NANO58406.2023.10231288
  5. F. Pavanello, C. Marchand, I. O'Connor et al., NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS, 2023 IEEE European Test Symposium (ETS), Venezia, Italy, 2023, pp. 1-6, doi: 10.1109/ETS56758.2023.10173974.
  6. P.A. Matrangolo, C. Marchand, I. O'Connor, D. Navarro, Hardware Emulation of FeFET on FPGA, in proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2022), Pafos, Cyprus, July 2022. doi : 10.1109/ISVLSI54635.2022.00085
  7. A. Poittevin, C. Marchand, I. O’Connor, et. al., A Logic Cell Design and Routing Methodology Specific to VNWFET, in proceedings of the 20th Internationnal NEWCAS conference (NEWCAS 2022), Quebec city, june 2022. doi : 10.1109/NEWCAS52662.2022.9842100
  8. C. Maneux, C. Mukherjee, M. Deng, et al. Modelling of vertical and ferroelectric junctionless technology for efficient 3D neural network compute cube dedicated to embedded artificial intelligence. In proceedings of the 67th Annual IEEE International Electron Devices Meeting (IEDM) 2021, December 2021, San Francisco, USA. (invited paper), doi : 10.1109/IEDM19574.2021.9720572
  9. C. Marchand, I. O’Connor, M. Cantan, et. al. FeFET based Logic-in-Memory: an overview. In proceedings of the IEEE 16th International Conference on Design & Technology of Integrated System in Nanoscale Era (DTIS 2021), June 2021, online event, Apulia, Italy. doi : 10.1109/DTIS53253.2021.9505078
  10. A. Bosio, M. Cantan, C. Marchand, et al. Emerging Technologies: Challenges and Opportunities for Logic Synthesis. In proceedings of the 2021 IEEE 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), April 2021, online event, Vienna, Austria. doi : 10.1109/DDECS52668.2021.9417062
  11. M. Chhandak, M. Deng, F. Marc, et al. 3D logic cells design and results based on Vertical NWFET technology including tied compact model. 28th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC) 2020, Oct 2020, Salt Lake City (virtual), United States. doi: hal-03166674
  12. I. O’Connor, M. Cantan, C. Marchand et al., Prospects for energy-efficient edge computing with integrated HfO2-based ferroelectric devices, 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Verona, Italy, 2018, pp. 180-183. doi: 10.1109/VLSI-SoC.2018.8644809
  13. E. M. Benhani, C. Marchand, A. Aubert and L. Bossuet, On the security evaluation of the ARM TrustZone extension in a heterogeneous SoC, 30th IEEE International System-on-Chip Conference (SOCC), Munich, pp. 108-113, 2017. doi: 10.1109/SOCC.2017.8226018
  14. C. Marchand, L. Bossuet and A. Cherkaoui, Design and Characterization of the TERO-PUF on SRAM FPGAs, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, PA, 2016, pp. 134-139. doi: 10.1109/ISVLSI.2016.18
  15. C. Marchand, L. Bossuet, and A. Cherkaoui. Enhanced TERO-PUF Implementations and Characterization on FPGAs (Abstract Only). In Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA ’16), pp.282. New York, NY, USA, p-282, 2016. doi: https://doi.org/10.1145/2847263.2847298
  16. E. Jung, C. Marchand and L. Bossuet. Identification of embedded control units by state encoding and power consumption analysis. In Proceedings of the 30th Annual ACM Symposium on Applied Computing (SAC'15), pp. 1957-1959, 2015. doi: https://doi.org/10.1145/2695664.2695963
  17. C. Marchand, L. Bossuet and E. Jung, IP watermark verification based on power consumption analysis, 27th IEEE International System-on-Chip Conference (SOCC), Las Vegas, 2014, pp. 330-335, doi: 10.1109/SOCC.2014.6948949
Top Journal Book Chapter Keynotes Workshops and Posters

Book Chapter

  1. A. Poittevin et al. Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model In: Calimera A., Gaillardon PE., Korgaonkar K., Kvatinsky S., Reis R. (eds) VLSI-SoC: Design Trends. VLSI-SoC 2020. IFIP Advances in Information and Communication Technology, vol 621. Springer, Cham. doi : https://doi.org/10.1007/978-3-030-81641-4_14
  2. C. Marchand, L. Bossuet and K. Gaj, Ultra-Lightweight Implementation in Area of Block Ciphers In: Bossuet L., Torres L. (eds) Foundations of Hardware IP Protection, pp 177-203. Springer, Cham, 2017, doi : https://doi.org/10.1007/978-3-319-50380-6_9
  3. L. Bossuet and C. Marchand, Side Channel Analysis, an Efficient Ally for IP Protection In: Bossuet L., Torres L. (eds) Foundations of Hardware IP Protection, pp 85-104. Springer, Cham, 2017, doi: https://doi.org/10.1007/978-3-319-50380-6_5
Top Journal Conferences Keynotes Workshops and Posters

Invited presentations and keynotes

  1. C. Marchand, Exploration de la mémoire hybride TC-MEM multi-bit pour des applications de sécurité, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH), Lavey-les-bains, Switzerland, February 2023
  2. C. Marchand, Cryptographic implementation using Ferroelectric transistor, Journée Thématique : Sécurité matérielle et architectures de calcul en mémoire, GDR SoC² et sécurité informatique, Paris, France, Octobre 2022.
  3. C. Marchand, Implementation of hardware security primitives with emerging non-volatile technologies, Séminaire fil rouge du laboratoire ETIS, Cergy Pontoise, July 2022.
  4. C. Marchand, Mémoire ferroélectrique hybride TC-MEM et implémentation de SBOX cryptographique, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH), Chamonix, Juin 2022.
  5. C. Marchand, System architectures and new computing paradigms: FeFET opportunities for Secure and reconfigurable processor, Journée Thématique : In-Memory Computing: from device to programming model, GDR SoC², February 2021
  6. C. Marchand, Sécurité dans l’Internet des Objets : de la communication aux capteurs, Journée Thématique : Systèmes Embarqués et Objets Communicants, GDR SoC² et RSD, Paris, France, 2019
  7. C. Marchand, Sécurité dans l’Internet des Objets : de la communication aux capteurs, Journée thématique « Sécurité des systèmes électroniques et communicants », GDR ondes, Paris, France, 2019
  8. C. Marchand, Area-oriented comparison of lightweight block ciphers implemented in hardware for the activation mechanism in an anti-counterfeiting scheme, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH), Saint Malo, France, 2018
  9. C. Marchand, Conception de matériels salutaires pour lutter contre la contrefaçon et le vol de circuits intégrés, Séminaire DGA, IRISA, Renne, France, 2017
Top Journal Conferences Book Chapter Workshops and Posters

Workshops and posters

  1. P. Jimenez, R. Cardoso, M. de Queiroz, M. Abdalla, C. Zrounba, U. Rührmair, C. Marchand, X. Letartre, and F. Pavanello, Physical Unclonable Function Based on Symmetric Microring Resonator Arrays, in Frontiers in Optics + Laser Science 2023 (FiO, LS), Technical Digest Series (Optica Publishing Group, 2023), doi: https://doi.org/10.1364/FIO.2023.JTu4A.82
  2. C. Marchand, Exploring FeFET based hybrid TC-MEM memory, High-k workshop, Dresden, Germany, September 2022
  3. A. Nicolas, C. Marchand, D. Navarro, Plateforme d’émulation d’opérateurs non volatiles sur FPGA, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH), Chamonix, France, June 2022 (Poster)
  4. P.A. Matrangolo, C. Marchand, D. Navarro, Hardware Emulation De FeFET Sur FPGA, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH), Chamonix, France, June 2022 (Poster)
  5. C. Marchand, I. O’Connor, S. Slesazeck and T. Mikolajick, In-Memory implementation of SBoxes using Ferroelectric transistors, 2022 Workshop on Cryptographic architecture, Cryptarchi 2022, Porquerolles, France. (pdf)
  6. C. Marchand, I. O’Connor, M. Cantan, TC-MEM improvement: TCAM and normal memory in the same circuit, 2022 Workshop on Ferroelectronics, online event March 2022.
  7. C. Marchand. SECure and Reconfigurable processor using Emerging Technology, Workshop interdisciplinaire sur la sécurité globale (WISG) 2022, online event, (poster, Invited).
  8. C Maneux, M Chhandak, M Deng, et al. Why neuromorphic computing need novel 3D technologies? A view from FVLLMONTI European project consortium, High Performance Embedded Architecture and Compilation, Computing Systems Week, (HiPEAC CSW) Autumn 2021, Lyon, France (Invited), url : https://hal.archives-ouvertes.fr/hal-03408071
  9. M. Cantan, M. Traiola, C. Marchand, D. Deleruyelle, A. Bosio, I. O’Connor. Performance evaluation of integrated ferroelectrics: from device to system. Poster, Colloque nationale du GDR SoC², 2021
  10. C. Marchand, Internet of things security: review from communication to sensor. Cryptarchi 2019, Prague, Czech Republic, June 23-26, 2019
  11. C. Zrounba, S. Le Beux, I. O’Connor, A. Bosio, C. Marchand. OpticALL²: On-Chip Optical ALL-to-ALL communication. Poster, Colloque nationale du GDR SoC², 2019
  12. M. Cantan, I. O’Connor, D. Deleruyelle, C. Marchand, A. Bosio, S. Le Beux and P.E. Polet. In-memory computing with integrated ferroelectrics for energy-efficient edge devices. Poster, Colloque nationale du GDR SoC², 2019
  13. A. Poittevin, S. Le-Beux, C. Marchand, A. Bosio, I. O’Connor. Co-optimization flow of Vertical Nanowires Field-Effect Transistors based standard cells. Poster, Colloque nationale du GDR SoC², 2019
  14. L. Del Bosque, S. Le Beux, C. Marchand, A. Bosio, I. O’Connor . Hardware Emulation Platform for Nanophotonic Interconnects. Poster, Colloque nationale du GDR SoC², 2019
  15. A. Poittevin, I. O'Connor, S. Le Beux, C. Marchand, Cellules logiques économes en énergie basées sur de Vnw-FET, Présentation orale et poster doctorant, École d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH), Louvain-La-Neuve, Belgique, 2019
  16. M. Cantan,I. O’Connor,C. Marchand, D. Deleruyelle, Energy-efficient edge computing with integrated ferroelectric devices Présentation orale et poster doctorant, École d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH), Louvain-La-Neuve, Belgique, 2019
  17. N. Bochard, C. Marchand, O. Peťura, L. Bossuet, V. Fischer. Evariste III: A new multi-FPGA system for fair benchmarking of hardware dependent cryptographic primitives Workshop on Cryptographic Hardware and Embedded Systems, CHES 2015, Sep 2015, st-malo, France. 2015
  18. C. Marchand, A. Cherkaoui and L. Bossuet. Enhanced TERO-PUF design and characterization with FPGA Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, TRUDEVICE Workshop of Date 2015), Grenoble, France. hal-01382969, 2015
  19. C. Marchand and L. Bossuet, E. Jung. Verification of IP Watermark using Correlation Analysis International Workshops on Cryptographic Architectures Embedded in Reconfigurable Devices (Cryptarchi 2014), Annecy, France. pp.13. ⟨ujm-01011317⟩, 2014
  20. C. Marchand and L. Bossuet. Correlation Analysis of the Power Consumption applied to IP watermark verification Colloque national du GDR SOC-SIP, Paris, France. ⟨ujm-01015290⟩, 2014
Top Journal Conferences Book Chapter Keynotes

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cedric.marchand@ec-lyon.fr

Address

Lyon Institute of Nanotechnology (INL)
Ecole Centrale de Lyon – University of Lyon
Building F7, Office 209
36, avenue Guy de Collongue
F-69134 Ecully cedex, France
Phone : +33 472 186 038

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